1. Field of the Invention
Embodiments of the invention relate generally to non-volatile memory devices. More particularly, embodiments of the invention relate to technologies adapted to reduce a coupling effect between storage elements in the non-volatile memory devices.
A claim of priority is made to Korean Patent Application No. 2006-0096711, filed on Sep. 30, 2006, the disclosure of which is hereby incorporated by reference in its entirety.
2. Description of Related Art
FIG. 1 is a block diagram of a conventional memory array 10 including a plurality of sub-memory arrays. Referring to FIG. 1, memory array 10 includes a plurality of sub-memory arrays including a first sub-memory array 11, a second sub-memory array 13, and a plurality of strapping lines 12 formed in a bit line direction (or a column direction) between adjacent sub-memory arrays. Each of sub-memory arrays 11 and 13 includes a plurality of even bit lines and a plurality of odd bit lines.
FIG. 2 is a block diagram of a non-volatile memory device 20 including memory array 10 illustrated in FIG. 1. Referring to FIG. 2, non-volatile memory device 20 includes memory array 10, a row decoder 12, a control signal generation circuit 14, a switching block 16, and a page buffer 18. Sub-memory array 11 in memory array 10 includes even bit lines BLe1 and BLe2 and odd bit lines BLo1 and BLo2. Similarly, sub-memory array 13 in memory array 10 includes even bit lines BLe1′ and BLe2′ and odd bit lines BLo1′ and BLo2′. Cell strings 15 are respectively connected with even bit lines BLe1, BLe2, BLe1′ and BLe2′ and odd bit lines BLo1 and BLo2, BLo1′, and BLo2′. Each of cell strings 15 typically comprises a NAND string.
Each of cell strings 15 includes a first selection transistor, a second selection transistor, and a plurality of NAND flash electrically erasable and programmable read only memory (EEPROM) cells connected in series between the first and second selection transistors. For explanation purposes, memory cells connected to even bit lines may be referred to throughout this written description as “even memory cells” and memory cells connected to odd bit lines may be referred to as “odd memory cells.” Each NAND flash EEPROM cell included in each cell string 15 is formed in a P-type region or an N-type region. The P-type region is typically formed within an N-type well formed in a P-type substrate and the N-type region is typically formed within a P-type well formed in an N-type substrate.
Strapping lines 12 include a strapping line for applying a voltage to the P-type region (or the N-type region), a strapping line for applying a voltage to a common source line, a bit line connected with dummy memory cells, and a strapping line for contacts. Each of strapping lines 12 is typically formed with a structure similar to bit lines connected with respective cell strings 15.
The memory cells illustrated in memory array 10 are multi-level cells. In other words, the memory cells can be programmed to store more than one bit of data by adjusting the respective threshold voltages of the memory cells to different levels. For illustration purposes, multi-level memory cells for storing 2-bit data will be described. However, some multi-level cells can store more than 2 bits. In the 2-bit data, an upper bit will be referred to as 2nd page data and a lower bit will be referred to as 1st page data.
FIG. 3 is a block diagram illustrating one order in which memory cells in sub-memory array 11 or 13 illustrated in FIG. 2 can be programmed. Here, memory cells are programmed in units of odd and even pages. In other words, even memory cells connected to the same word line are programmed at the same time and odd memory cells connected to the same word line are programmed at the same time. A method of programming memory cells in sub-memory array 11 or 13 is described below with reference to FIGS. 1 through 3.
As shown in FIG. 2, switching block 16 comprises switches 16-1 through 16-8 and page buffer 18 includes storage elements 18-1 through 18-4. Switches 16-1, 16-3, 16-5, and 16-7 respectively connect even bit lines BLe1, BLe2, BLe1′, and BLe2′ in sub-memory array 11 and 13 with respective data storage elements 18-1, 18-2, 18-3 and 18-4 in response to a first control signal output from control signal generation circuit 14. Similarly, switches 16-2, 164, 16-6, and 16-8 in switching block 16 respectively connect odd bit lines BLo1, BLo2, BLo1′, and BLo2′ in sub-memory array 11 and 13 with respective data storage elements 18-1, 18-2, 18-3, and 18-4 in response to a second control signal output from control signal generation circuit 14. Accordingly, as illustrated in FIG. 3, a program operation or read operation can be performed on odd memory cells or even memory cells according to the first and second control signals. The memory cells are programmed in an order indicated by the reference numerals 0 through 11. For example, 1st page data is programmed in memory cells connected to odd bit lines, as indicated by reference numerals “0”. Then 1st page data is programmed in memory cells connected to even bit lines, as indicated by reference numerals “1”. Next, 2nd page data is programmed in memory cells connected to odd bit lines as indicated by reference numeral “2”, and so on.
FIG. 4 is a conceptual diagram illustrating a coupling effect between conventional memory cells. The coupling effect occurs where a threshold voltage change ΔVx of one or more memory cells causes a threshold voltage change in other, e.g., adjacent memory cells. For example, where even memory cells in FIG. 4 are programmed, a threshold voltage of an odd memory cell in FIG. 4 may change due to coupling capacitances Cx between the even memory cells and the odd memory cell.
The magnitude of the coupling effect can be roughly quantified in proportion to a combination of coupling capacitances Cx and the threshold voltage change ΔVx of the even memory cells. For example, the magnitude of the coupling effect can be roughly quantified as 2CxΔVx.
Due to the coupling effect, additional program operations may be required to correct threshold voltage distributions in the memory cells. Unfortunately, however, these additional program operations tend to stress the memory cells. As a result, the reliability of the memory cells may deteriorate.
FIGS. 5A through 5D illustrate threshold voltage distributions for memory cells affected by coupling capacitance when programmed using a conventional programming method. Reference numerals shown in FIGS. 5A through 5D indicate the order in which memory cells are programmed.
Referring to FIG. 5A, where selected even memory cells connected to a word line WL0 are programmed from a threshold voltage state “11” to a threshold voltage state “01” in a program operation indicated by reference numeral “3”, a threshold voltage of a memory cell labeled “worst case cell” is affected by a threshold voltage change ΔVx1 of the selected even memory cells. In FIG. 5A, the labels Vo10, Vo00, and Vo01 denote program verify voltage levels used to verify that memory cells are properly programmed.
Referring to FIG. 5B, where even memory cells connected to a word line WL1 are programmed in a program operation indicated by reference numeral “7”, the threshold voltage of the memory cell labeled “worst case cell” is affected by threshold voltage changes ΔVx1 of horizontally adjacent memory cells, by a threshold voltage change ΔVy1 of a vertically adjacent memory cell and threshold voltage changes ΔVXy1 of diagonally adjacent memory cells.
The memory cells in FIGS. 5C and 5D are programmed in a different order than the memory cells in FIGS. 5A and 5B. Referring to FIG. 5C, where selected even memory cells connected to word line WL0 are programmed from threshold voltage state “11” to a threshold voltage state “10” in an operation indicated by reference numeral “5”, for example, the threshold voltage of the memory cell labeled “worst case cell” is affected by threshold voltage changes ΔVx2 of the selected even memory cells.
Referring to FIG. 5D, where selected even memory cells connected to word line WL1 are programmed in an operation indicated by reference numeral “7”, the threshold voltage of the memory cell labeled “worst case cell” is affected by threshold voltage changes ΔVx2 of horizontally adjacent even memory cells, by a threshold voltage change ΔVy2 of a vertically adjacent odd memory cell, and threshold voltage changes ΔVxy2 of diagonally adjacent memory cells.
Based on the above description related to FIGS. 5A through 5D, the threshold voltage of the memory cell labeled “worst case cell” is affected by threshold voltage changes ΔVx1, ΔVx2, and ΔVxy2, even when the programming order is varied. As a result, the performance and reliability of the memory cells tends to deteriorate.